HAL DMA constants migration ¶

This section provides information about the HAL DMA constants migration.

HAL DMA error code ¶

HAL1	HAL2
#define HAL_DMA_ERROR_NONE	#define HAL_DMA_ERROR_NONE
#define HAL_DMA_ERROR_DTE	#define HAL_DMA_ERROR_DTE
#define HAL_DMA_ERROR_ULE	#define HAL_DMA_ERROR_ULE
#define HAL_DMA_ERROR_USE	#define HAL_DMA_ERROR_USE
#define HAL_DMA_ERROR_TO	#define HAL_DMA_ERROR_TO
#define HAL_DMA_ERROR_TE	#define HAL_DMA_ERROR_TE
#define HAL_DMA_ERROR_SYNC	#define HAL_DMA_DMAMUX_ERROR_SYNC
#define HAL_DMA_ERROR_REQGEN	#define HAL_DMA_DMAMUX_ERROR_REQGEN
#define HAL_DMA_ERROR_TIMEOUT #define HAL_DMA_ERROR_NO_XFER #define HAL_DMA_ERROR_BUSY #define HAL_DMA_ERROR_INVALID_CALLBACK #define HAL_DMA_ERROR_NOT_SUPPORTED	Removed; These kinds of logical errors are reported by the direct function return.

HAL DMA queue error code ¶

HAL1	HAL2
#define HAL_DMA_QUEUE_ERROR_NONE #define HAL_DMA_QUEUE_ERROR_BUSY #define HAL_DMA_QUEUE_ERROR_EMPTY #define HAL_DMA_QUEUE_ERROR_UNSUPPORTED #define HAL_DMA_QUEUE_ERROR_INVALIDTYPE #define HAL_DMA_QUEUE_ERROR_OUTOFRANGE #define HAL_DMA_QUEUE_ERROR_NOTFOUND	Removed; HAL2 does not expose queue-specific error codes. Errors are returned directly by the API.

HAL1

HAL2

                #define HAL_DMA_QUEUE_ERROR_NONE
#define HAL_DMA_QUEUE_ERROR_BUSY
#define HAL_DMA_QUEUE_ERROR_EMPTY
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE
#define HAL_DMA_QUEUE_ERROR_NOTFOUND

               

Removed; HAL2 does not expose queue-specific error codes. Errors are returned directly by the API.

HAL DMA transfer mode ¶

HAL1	HAL2
#define DMA_NORMAL #define DMA_LINKEDLIST_NORMAL #define DMA_LINKEDLIST_CIRCULAR	typedef enum { HAL_DMA_XFER_MODE_DIRECT, HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR, HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR } hal_dma_xfer_mode_t;
#define DMA_NORMAL #define DMA_CIRCULAR	#define LL_DMA_MODE_NORMAL #define LL_DMA_MODE_CIRCULAR

HAL1

HAL2

                #define DMA_NORMAL
#define DMA_LINKEDLIST_NORMAL
#define DMA_LINKEDLIST_CIRCULAR

               

                typedef enum
{
  HAL_DMA_XFER_MODE_DIRECT,
  HAL_DMA_XFER_MODE_LINKEDLIST_LINEAR,
  HAL_DMA_XFER_MODE_LINKEDLIST_CIRCULAR
} hal_dma_xfer_mode_t;

               

                #define DMA_NORMAL
#define DMA_CIRCULAR

                #define LL_DMA_MODE_NORMAL
#define LL_DMA_MODE_CIRCULAR

HAL DMA data alignment ¶

HAL1	HAL2
#define DMA_DATA_RIGHTALIGN_ZEROPADDED #define DMA_DATA_RIGHTALIGN_LEFTTRUNC #define DMA_DATA_RIGHTALIGN_SIGNEXT #define DMA_DATA_LEFTALIGN_RIGHTTRUNC	typedef enum { HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO, HAL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN } hal_dma_dest_data_trunc_padd_t;
#define DMA_DATA_PACK #define DMA_DATA_UNPACK	typedef enum { HAL_DMA_DEST_DATA_PRESERVED, HAL_DMA_DEST_DATA_PACKED_UNPACKED } hal_dma_dest_data_pack_t;

HAL1

HAL2

                #define DMA_DATA_RIGHTALIGN_ZEROPADDED
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC

                #define DMA_DATA_RIGHTALIGN_SIGNEXT
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC

                typedef enum
{
  HAL_DMA_DEST_DATA_TRUNC_LEFT_PADD_ZERO,

  HAL_DMA_DEST_DATA_TRUNC_RIGHT_PADD_SIGN

} hal_dma_dest_data_trunc_padd_t;

                #define DMA_DATA_PACK
#define DMA_DATA_UNPACK

                typedef enum
{
  HAL_DMA_DEST_DATA_PRESERVED,
  HAL_DMA_DEST_DATA_PACKED_UNPACKED
} hal_dma_dest_data_pack_t;

               

HAL DMA data exchange ¶

HAL1	HAL2
#define DMA_EXCHANGE_NONE #define DMA_EXCHANGE_SRC_BYTE	typedef enum { HAL_DMA_SRC_BYTE_PRESERVED, HAL_DMA_SRC_BYTE_EXCHANGED } hal_dma_src_byte_exchange_t;
#define DMA_EXCHANGE_NONE #define DMA_EXCHANGE_DEST_BYTE	typedef enum { HAL_DMA_DEST_BYTE_PRESERVED, HAL_DMA_DEST_BYTE_EXCHANGED } hal_dma_dest_byte_exchange_t;
#define DMA_EXCHANGE_NONE #define DMA_EXCHANGE_DEST_HALFWORD	typedef enum { HAL_DMA_DEST_HALFWORD_PRESERVED, HAL_DMA_DEST_HALFWORD_EXCHANGED } hal_dma_dest_halfword_exchange_t;

HAL1

HAL2

                #define DMA_EXCHANGE_NONE
#define DMA_EXCHANGE_SRC_BYTE

                typedef enum
{
  HAL_DMA_SRC_BYTE_PRESERVED,
  HAL_DMA_SRC_BYTE_EXCHANGED
} hal_dma_src_byte_exchange_t;

               

                #define DMA_EXCHANGE_NONE
#define DMA_EXCHANGE_DEST_BYTE

                typedef enum
{
  HAL_DMA_DEST_BYTE_PRESERVED,
  HAL_DMA_DEST_BYTE_EXCHANGED
} hal_dma_dest_byte_exchange_t;

               

                #define DMA_EXCHANGE_NONE
#define DMA_EXCHANGE_DEST_HALFWORD

                typedef enum
{
  HAL_DMA_DEST_HALFWORD_PRESERVED,
  HAL_DMA_DEST_HALFWORD_EXCHANGED
} hal_dma_dest_halfword_exchange_t;

               

HAL DMA trigger polarity ¶

HAL1	HAL2
#define DMA_TRIG_POLARITY_MASKED #define DMA_TRIG_POLARITY_RISING #define DMA_TRIG_POLARITY_FALLING	typedef enum { HAL_DMA_TRIGGER_POLARITY_MASKED, HAL_DMA_TRIGGER_POLARITY_RISING, HAL_DMA_TRIGGER_POLARITY_FALLING } hal_dma_trigger_polarity_t;

HAL1

HAL2

                #define DMA_TRIG_POLARITY_MASKED
#define DMA_TRIG_POLARITY_RISING
#define DMA_TRIG_POLARITY_FALLING

               

                typedef enum
{
  HAL_DMA_TRIGGER_POLARITY_MASKED,
  HAL_DMA_TRIGGER_POLARITY_RISING,
  HAL_DMA_TRIGGER_POLARITY_FALLING
} hal_dma_trigger_polarity_t;

               

HAL DMA trigger mode ¶

HAL1	HAL2
#define DMA_TRIGM_BLOCK_TRANSFER #define DMA_TRIGM_REPEATED_BLOCK_TRANSFER #define DMA_TRIGM_LLI_LINK_TRANSFER #define DMA_TRIGM_SINGLE_BURST_TRANSFER	typedef enum { HAL_DMA_TRIGGER_BLOCK_TRANSFER, HAL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER, HAL_DMA_TRIGGER_NODE_TRANSFER, HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER } hal_dma_trigger_mode_t;

HAL1

HAL2

                #define DMA_TRIGM_BLOCK_TRANSFER
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER
#define DMA_TRIGM_LLI_LINK_TRANSFER
#define DMA_TRIGM_SINGLE_BURST_TRANSFER

               

                typedef enum
{
  HAL_DMA_TRIGGER_BLOCK_TRANSFER,
  HAL_DMA_TRIGGER_REPEATED_BLOCK_TRANSFER,
  HAL_DMA_TRIGGER_NODE_TRANSFER,
  HAL_DMA_TRIGGER_SINGLE_BURST_TRANSFER
} hal_dma_trigger_mode_t;

               

HAL DMA trigger selection ¶

HAL_ prefix has been added to each define in HAL2.

HAL1	HAL2
#define GPDMA1_TRIGGER_EXTI_LINE0 #define GPDMA1_TRIGGER_EXTI_LINE1 . . #define GPDMA1_TRIGGER_GPDMA1_CH0_TCF #define GPDMA1_TRIGGER_GPDMA1_CH1_TCF . . #define LPDMA1_TRIGGER_TIM2_TRGO #define LPDMA1_TRIGGER_TIM15_TRGO	typedef enum { HAL_GPDMA1_TRIGGER_EXTI0, HAL_GPDMA1_TRIGGER_EXTI1, . . HAL_GPDMA1_TRIGGER_GPDMA1_CH0_TC, HAL_GPDMA1_TRIGGER_GPDMA1_CH1_TC, . . HAL_LPDMA1_TRIGGER_TIM2_TRGO, HAL_LPDMA1_TRIGGER_TIM15_TRGO } hal_dma_trigger_source_t;

HAL1

HAL2

                #define GPDMA1_TRIGGER_EXTI_LINE0
#define GPDMA1_TRIGGER_EXTI_LINE1
           .
           .
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF
           .
           .
#define LPDMA1_TRIGGER_TIM2_TRGO
#define LPDMA1_TRIGGER_TIM15_TRGO

               

                typedef enum
{
HAL_GPDMA1_TRIGGER_EXTI0,
HAL_GPDMA1_TRIGGER_EXTI1,
           .
           .
HAL_GPDMA1_TRIGGER_GPDMA1_CH0_TC,
HAL_GPDMA1_TRIGGER_GPDMA1_CH1_TC,
           .
           .
HAL_LPDMA1_TRIGGER_TIM2_TRGO,
HAL_LPDMA1_TRIGGER_TIM15_TRGO
} hal_dma_trigger_source_t;

               

HAL DMA transfer allocated port ¶

HAL1	HAL2
#define DMA_SRC_ALLOCATED_PORT0 #define DMA_DEST_ALLOCATED_PORT0 #define DMA_LINK_ALLOCATED_PORT0 #define DMA_SRC_ALLOCATED_PORT1 #define DMA_DEST_ALLOCATED_PORT1 #define DMA_LINK_ALLOCATED_PORT1	typedef enum { HAL_DMA_PORT0, HAL_DMA_PORT1 } hal_dma_port_t;

HAL1

HAL2

                #define DMA_SRC_ALLOCATED_PORT0
#define DMA_DEST_ALLOCATED_PORT0
#define DMA_LINK_ALLOCATED_PORT0

               

                #define DMA_SRC_ALLOCATED_PORT1
#define DMA_DEST_ALLOCATED_PORT1
#define DMA_LINK_ALLOCATED_PORT1

               

                typedef enum
{
  HAL_DMA_PORT0,

  HAL_DMA_PORT1

} hal_dma_port_t;

HAL DMA link step mode ¶

HAL1	HAL2
#define DMA_LSM_FULL_EXECUTION #define DMA_LSM_1LINK_EXECUTION	typedef enum { HAL_DMA_LINKEDLIST_EXECUTION_Q, HAL_DMA_LINKEDLIST_EXECUTION_NODE } hal_dma_linkedlist_execution_mode_t;

HAL DMA transfer event mode ¶

HAL1	HAL2
Direct transfer event mode #define DMA_TCEM_BLOCK_TRANSFER #define DMA_TCEM_REPEATED_BLOCK_TRANSFER	typedef enum { HAL_DMA_DIRECT_XFER_EVENT_BLOCK, HAL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK } hal_dma_direct_xfer_event_mode_t;
Linkedlist transfer event mode #define DMA_TCEM_BLOCK_TRANSFER #define DMA_TCEM_REPEATED_BLOCK_TRANSFER #define DMA_TCEM_EACH_LL_ITEM_TRANSFER #define DMA_TCEM_LAST_LL_ITEM_TRANSFER	typedef enum { HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK, HAL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK, HAL_DMA_LINKEDLIST_XFER_EVENT_NODE, HAL_DMA_LINKEDLIST_XFER_EVENT_Q } hal_dma_linkedlist_xfer_event_mode_t;

HAL1

HAL2

Direct transfer event mode

                #define DMA_TCEM_BLOCK_TRANSFER
#define DMA_TCEM_REPEATED_BLOCK_TRANSFER

                typedef enum
{
  HAL_DMA_DIRECT_XFER_EVENT_BLOCK,
  HAL_DMA_DIRECT_XFER_EVENT_REPEATED_BLOCK
} hal_dma_direct_xfer_event_mode_t;

               

Linkedlist transfer event mode

                #define DMA_TCEM_BLOCK_TRANSFER
#define DMA_TCEM_REPEATED_BLOCK_TRANSFER
#define DMA_TCEM_EACH_LL_ITEM_TRANSFER
#define DMA_TCEM_LAST_LL_ITEM_TRANSFER

               

                typedef enum
{
  HAL_DMA_LINKEDLIST_XFER_EVENT_BLOCK,
  HAL_DMA_LINKEDLIST_XFER_EVENT_REPEATED_BLOCK,
  HAL_DMA_LINKEDLIST_XFER_EVENT_NODE,
  HAL_DMA_LINKEDLIST_XFER_EVENT_Q
} hal_dma_linkedlist_xfer_event_mode_t;

               

HAL DMA channel attributes ¶

HAL1	HAL2
#define DMA_CHANNEL_PRIV	#define HAL_DMA_PRIV
#define DMA_CHANNEL_NPRIV	#define HAL_DMA_NPRIV
#define DMA_CHANNEL_SEC	#define HAL_DMA_SEC
#define DMA_CHANNEL_NSEC	#define HAL_DMA_NSEC
#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED #define DMA_CHANNEL_ATTRIBUTE_LOCKED	typedef enum { HAL_DMA_UNLOCKED, HAL_DMA_LOCKED } hal_dma_attr_lock_status_t;

HAL DMA channel source destination attributes ¶

In HAL1, source and destination security attributes were defined separately.

In HAL2, these attributes are mutually exclusive: selecting one implies the other is not selected.

HAL1	HAL2
#define DMA_CHANNEL_SRC_SEC #define DMA_CHANNEL_DEST_NSEC #define DMA_CHANNEL_DEST_SEC #define DMA_CHANNEL_SRC_NSEC	#define HAL_DMA_SEC_ITEM_SRC #define HAL_DMA_SEC_ITEM_DEST

HAL DMA request selection ¶

HAL_ prefix has been added to each define in HAL2.

HAL1	HAL2
#define GPDMA1_REQUEST_ADC1 #define GPDMA1_REQUEST_ADC4 . . #define GPDMA1_REQUEST_USART3_RX #define GPDMA1_REQUEST_USART3_TX . . #define LPDMA1_REQUEST_LPTIM3_UE #define DMA_REQUEST_SW	typedef enum { HAL_GPDMA1_REQUEST_ADC1, HAL_GPDMA1_REQUEST_ADC4, . . HAL_GPDMA1_REQUEST_USART3_RX, HAL_GPDMA1_REQUEST_USART3_TX, . . HAL_LPDMA1_REQUEST_LPTIM3_UE, HAL_DMA_REQUEST_SW } hal_dma_request_source_t;

HAL1

HAL2

                #define GPDMA1_REQUEST_ADC1
#define GPDMA1_REQUEST_ADC4
             .
             .
#define GPDMA1_REQUEST_USART3_RX
#define GPDMA1_REQUEST_USART3_TX
             .
             .
#define LPDMA1_REQUEST_LPTIM3_UE
#define DMA_REQUEST_SW

               

                typedef enum
{
  HAL_GPDMA1_REQUEST_ADC1,
  HAL_GPDMA1_REQUEST_ADC4,
       .
       .
  HAL_GPDMA1_REQUEST_USART3_RX,
  HAL_GPDMA1_REQUEST_USART3_TX,
       .
       .
  HAL_LPDMA1_REQUEST_LPTIM3_UE,
  HAL_DMA_REQUEST_SW
} hal_dma_request_source_t;

               

HAL DMA block request ¶

HAL1	HAL2
#define DMA_BREQ_SINGLE_BURST #define DMA_BREQ_BLOCK	typedef enum { HAL_DMA_HARDWARE_REQUEST_BURST, HAL_DMA_HARDWARE_REQUEST_BLOCK } hal_dma_hardware_request_mode_t;

HAL DMA transfer direction ¶

HAL1	HAL2
#define DMA_PERIPH_TO_MEMORY #define DMA_MEMORY_TO_PERIPH #define DMA_MEMORY_TO_MEMORY	typedef enum { HAL_DMA_DIRECTION_MEMORY_TO_MEMORY, HAL_DMA_DIRECTION_PERIPH_TO_MEMORY, HAL_DMA_DIRECTION_MEMORY_TO_PERIPH } hal_dma_direction_t;

HAL1

HAL2

                #define DMA_PERIPH_TO_MEMORY
#define DMA_MEMORY_TO_PERIPH
#define DMA_MEMORY_TO_MEMORY

               

                typedef enum
{
  HAL_DMA_DIRECTION_MEMORY_TO_MEMORY,
  HAL_DMA_DIRECTION_PERIPH_TO_MEMORY,
  HAL_DMA_DIRECTION_MEMORY_TO_PERIPH
} hal_dma_direction_t;

               

HAL DMA source increment mode ¶

HAL1	HAL2
#define DMA_SINC_FIXED #define DMA_MINC_DISABLE #define DMA_SINC_INCREMENTED #define DMA_MINC_ENABLE	typedef enum { HAL_DMA_SRC_ADDR_FIXED, HAL_DMA_SRC_ADDR_INCREMENTED } hal_dma_src_addr_increment_t;

HAL DMA destination increment mode ¶

HAL1	HAL2
#define DMA_DINC_FIXED #define DMA_PINC_DISABLE #define DMA_DINC_INCREM #define DMA_PINC_ENABLE	typedef enum { HAL_DMA_DEST_ADDR_FIXED, HAL_DMA_DEST_ADDR_INCREMENTED } hal_dma_dest_addr_increment_t;

HAL DMA source data width ¶

HAL1	HAL2
#define DMA_SRC_DATAWIDTH_BYTE #define DMA_MDATAALIGN_BYTE #define DMA_SRC_DATAWIDTH_HALFWORD #define DMA_MDATAALIGN_HALFWORD #define DMA_SRC_DATAWIDTH_WORD #define DMA_MDATAALIGN_WORD	typedef enum { HAL_DMA_SRC_DATA_WIDTH_BYTE, HAL_DMA_SRC_DATA_WIDTH_HALFWORD, HAL_DMA_SRC_DATA_WIDTH_WORD } hal_dma_src_data_width_t;

HAL1

HAL2

                #define DMA_SRC_DATAWIDTH_BYTE
#define DMA_MDATAALIGN_BYTE

                #define DMA_SRC_DATAWIDTH_HALFWORD
#define DMA_MDATAALIGN_HALFWORD

                #define DMA_SRC_DATAWIDTH_WORD
#define DMA_MDATAALIGN_WORD

                typedef enum
{
  HAL_DMA_SRC_DATA_WIDTH_BYTE,

  HAL_DMA_SRC_DATA_WIDTH_HALFWORD,

  HAL_DMA_SRC_DATA_WIDTH_WORD

} hal_dma_src_data_width_t;

HAL DMA destination data width ¶

HAL1	HAL2
#define DMA_DEST_DATAWIDTH_BYTE #define DMA_PDATAALIGN_BYTE #define DMA_DEST_DATAWIDTH_HALFWORD #define DMA_PDATAALIGN_HALFWORD #define DMA_DEST_DATAWIDTH_WORD #define DMA_PDATAALIGN_WORD	typedef enum { HAL_DMA_DEST_DATA_WIDTH_BYTE, HAL_DMA_DEST_DATA_WIDTH_HALFWORD, HAL_DMA_DEST_DATA_WIDTH_WORD } hal_dma_dest_data_width_t;

HAL1

HAL2

                #define DMA_DEST_DATAWIDTH_BYTE
#define DMA_PDATAALIGN_BYTE

                #define DMA_DEST_DATAWIDTH_HALFWORD
#define DMA_PDATAALIGN_HALFWORD

                #define DMA_DEST_DATAWIDTH_WORD
#define DMA_PDATAALIGN_WORD

                typedef enum
{
  HAL_DMA_DEST_DATA_WIDTH_BYTE,

  HAL_DMA_DEST_DATA_WIDTH_HALFWORD,

  HAL_DMA_DEST_DATA_WIDTH_WORD

} hal_dma_dest_data_width_t;

HAL DMA priority level ¶

HAL1	HAL2
#define DMA_LOW_PRIORITY_LOW_WEIGHT #define DMA_LOW_PRIORITY_MID_WEIGHT #define DMA_LOW_PRIORITY_HIGH_WEIGHT #define DMA_HIGH_PRIORITY	typedef enum { HAL_DMA_PRIORITY_LOW_WEIGHT_LOW, HAL_DMA_PRIORITY_LOW_WEIGHT_MID, HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH, HAL_DMA_PRIORITY_HIGH, } hal_dma_priority_t;
#define DMA_PRIORITY_LOW #define DMA_PRIORITY_MEDIUM #define DMA_PRIORITY_HIGH #define DMA_PRIORITY_VERY_HIGH	typedef enum { HAL_DMA_PRIORITY_LOW, HAL_DMA_PRIORITY_MEDIUM, HAL_DMA_PRIORITY_HIGH, HAL_DMA_PRIORITY_VERY_HIGH, } hal_dma_priority_t;

HAL1

HAL2

                #define DMA_LOW_PRIORITY_LOW_WEIGHT
#define DMA_LOW_PRIORITY_MID_WEIGHT
#define DMA_LOW_PRIORITY_HIGH_WEIGHT
#define DMA_HIGH_PRIORITY

               

                typedef enum
{
  HAL_DMA_PRIORITY_LOW_WEIGHT_LOW,
  HAL_DMA_PRIORITY_LOW_WEIGHT_MID,
  HAL_DMA_PRIORITY_LOW_WEIGHT_HIGH,
  HAL_DMA_PRIORITY_HIGH,
} hal_dma_priority_t;

               

                #define DMA_PRIORITY_LOW
#define DMA_PRIORITY_MEDIUM
#define DMA_PRIORITY_HIGH
#define DMA_PRIORITY_VERY_HIGH

               

                typedef enum
{
  HAL_DMA_PRIORITY_LOW,
  HAL_DMA_PRIORITY_MEDIUM,
  HAL_DMA_PRIORITY_HIGH,
  HAL_DMA_PRIORITY_VERY_HIGH,
} hal_dma_priority_t;

               

HAL DMA flag definition ¶

HAL1	HAL2
#define DMA_FLAG_IDLE	#define LL_DMA_FLAG_IDLE
#define DMA_FLAG_TC	#define LL_DMA_FLAG_TC
#define DMA_FLAG_HT	#define LL_DMA_FLAG_HT
#define DMA_FLAG_DTE	#define LL_DMA_FLAG_DTE
#define DMA_FLAG_ULE	#define LL_DMA_FLAG_ULE
#define DMA_FLAG_USE	#define LL_DMA_FLAG_USE
#define DMA_FLAG_SUSP	#define LL_DMA_FLAG_SUSP
#define DMA_FLAG_TO	#define LL_DMA_FLAG_TO
#define DMA_FLAG_GI1 #define DMA_FLAG_TC1 #define DMA_FLAG_HT1 #define DMA_FLAG_TE1 . . #define DMA_FLAG_GI7 #define DMA_FLAG_TC7 #define DMA_FLAG_HT7 #define DMA_FLAG_TE7	#define LL_DMA_ISR_GIF1 #define LL_DMA_ISR_TCIF1 #define LL_DMA_ISR_HTIF1 #define LL_DMA_ISR_TEIF1 . . #define LL_DMA_ISR_GIF7 #define LL_DMA_ISR_TCIF7 #define LL_DMA_ISR_HTIF7 #define LL_DMA_ISR_TEIF7

HAL DMA interrupt enable definition ¶

HAL1	HAL2
#define DMA_IT_TC	#define LL_DMA_IT_TC #define LL_DMA_CCR_TCIE
#define DMA_IT_HT	#define LL_DMA_IT_HT #define LL_DMA_CCR_HTIE
#define DMA_IT_DTE	#define LL_DMA_IT_DTE
#define DMA_IT_ULE	#define LL_DMA_IT_ULE
#define DMA_IT_USE	#define LL_DMA_IT_USE
#define DMA_IT_SUSP	#define LL_DMA_IT_SUSP
#define DMA_IT_TO	#define LL_DMA_IT_TO
#define DMA_IT_TE	#define LL_DMA_CCR_TEIE

HAL DMA DMAMUX channel synchronisation ¶

HAL1	HAL2
#define HAL_DMAMUX_SYNC_NO_EVENT #define HAL_DMAMUX_SYNC_RISING #define HAL_DMAMUX_SYNC_FALLING #define HAL_DMAMUX_SYNC_RISING_FALLING	typedef enum { HAL_DMA_DMAMUX_SYNC_MASKED, HAL_DMA_DMAMUX_SYNC_RISING, HAL_DMA_DMAMUX_SYNC_FALLING, HAL_DMA_DMAMUX_SYNC_RISING_FALLING } hal_dma_dmamux_sync_polarity_t;

HAL1

HAL2

                #define HAL_DMAMUX_SYNC_NO_EVENT
#define HAL_DMAMUX_SYNC_RISING
#define HAL_DMAMUX_SYNC_FALLING
#define HAL_DMAMUX_SYNC_RISING_FALLING

               

                typedef enum
{
  HAL_DMA_DMAMUX_SYNC_MASKED,
  HAL_DMA_DMAMUX_SYNC_RISING,
  HAL_DMA_DMAMUX_SYNC_FALLING,
  HAL_DMA_DMAMUX_SYNC_RISING_FALLING
} hal_dma_dmamux_sync_polarity_t;

               

HAL DMA DMAMUX channel request generator source ¶

HAL1	HAL2
#define HAL_DMAMUX1_REQ_GEN_EXTI0 #define HAL_DMAMUX1_REQ_GEN_EXTI1 . . #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT #define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT	typedef enum { HAL_DMA1_DMAMUX1_REQGEN_EXTI0, HAL_DMA1_DMAMUX1_REQGEN_EXTI1, . . HAL_DMA1_DMAMUX1_REQGEN_MUX_CH1_EVT, HAL_DMA1_DMAMUX1_REQGEN_MUX_CH2_EVT } hal_dma_dmamux_reqgen_source_t;

HAL1

HAL2

                #define HAL_DMAMUX1_REQ_GEN_EXTI0
#define HAL_DMAMUX1_REQ_GEN_EXTI1
             .
             .
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

               

                typedef enum
{
  HAL_DMA1_DMAMUX1_REQGEN_EXTI0,
  HAL_DMA1_DMAMUX1_REQGEN_EXTI1,
       .
       .
  HAL_DMA1_DMAMUX1_REQGEN_MUX_CH1_EVT,
  HAL_DMA1_DMAMUX1_REQGEN_MUX_CH2_EVT
} hal_dma_dmamux_reqgen_source_t;

               

HAL DMA DMAMUX channel synchronisation source ¶

HAL1	HAL2
#define HAL_DMAMUX1_SYNC_EXTI0 #define HAL_DMAMUX1_SYNC_EXTI1 . . #define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT #define HAL_DMAMUX1_SYNC_TIM14_OC	typedef enum { HAL_DMA1_DMAMUX1_SYNC_EXTI0, HAL_DMA1_DMAMUX1_SYNC_EXTI1, . . HAL_DMA1_DMAMUX1_SYNC_MUX_CH2_EVT, HAL_DMA1_DMAMUX1_SYNC_TIM14_OC } hal_dma_dmamux_sync_source_t;

HAL1

HAL2

                #define HAL_DMAMUX1_SYNC_EXTI0
#define HAL_DMAMUX1_SYNC_EXTI1
             .
             .
#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
#define HAL_DMAMUX1_SYNC_TIM14_OC

               

                typedef enum
{
  HAL_DMA1_DMAMUX1_SYNC_EXTI0,
  HAL_DMA1_DMAMUX1_SYNC_EXTI1,
       .
       .
  HAL_DMA1_DMAMUX1_SYNC_MUX_CH2_EVT,
  HAL_DMA1_DMAMUX1_SYNC_TIM14_OC
} hal_dma_dmamux_sync_source_t;

               

HAL DMAMUX request generator polarity selection ¶

HAL1	HAL2
#define HAL_DMAMUX_REQ_GEN_NO_EVENT #define HAL_DMAMUX_REQ_GEN_RISING #define HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQ_GEN_RISING_FALLING	typedef enum { HAL_DMA_DMAMUX_REQGEN_MASKED, HAL_DMA_DMAMUX_REQGEN_RISING, HAL_DMA_DMAMUX_REQGEN_FALLING, HAL_DMA_DMAMUX_REQGEN_RISING_FALLING } hal_dma_dmamux_reqgen_polarity_t;

HAL1

HAL2

                #define HAL_DMAMUX_REQ_GEN_NO_EVENT
#define HAL_DMAMUX_REQ_GEN_RISING
#define HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQ_GEN_RISING_FALLING

               

                typedef enum
{
  HAL_DMA_DMAMUX_REQGEN_MASKED,
  HAL_DMA_DMAMUX_REQGEN_RISING,
  HAL_DMA_DMAMUX_REQGEN_FALLING,
  HAL_DMA_DMAMUX_REQGEN_RISING_FALLING
} hal_dma_dmamux_reqgen_polarity_t;

               